Next: AVR Options, Previous: ARC Options, Up: Submodel Options

#### 3.17.2 ARM Options

These ‘`-m`’ options are defined for Advanced RISC Machines (ARM) architectures:

`-mabi=`name
  Generate code for the specified ABI. Permissible values are: ‘`apcs-gnu`’, ‘`apcs-32`’, ‘`atpcs`’, ‘`aapcs`’, ‘`aapcs-linux`’ and ‘`iwmmxt`’.
`-mapcs-frame`
  Generate a stack frame that is compliant with the ARM Procedure Call Standard for all functions, even if this is not strictly necessary for correct execution of the code. Specifying `-fomit-frame-pointer` with this option will cause the stack frames not to be generated for leaf functions. The default is `-mno-apcs-frame`.
`-mapcs`
  This is a synonym for `-mapcs-frame`.
`-mapcs-stack-check`
  Generate code to check the amount of stack space available upon entry to every function (that actually uses some stack space). If there is insufficient space available then either the function ‘`__rt_stkovf_split_small`’ or ‘`__rt_stkovf_split_big`’ will be called, depending upon the amount of stack space required. The run time system is required to provide these functions. The default is `-mno-apcs-stack-check`, since this produces smaller code. However, the APCS-32 ABI has `-mapcs-stack-check` as default except when module code is generated with `-mmodule`.
`-mmodule`
  Generate code suited for building RISC OS modules. All writable data are accessed via an offset determined by the value at R10-536. This is only supported for APCS-32 ABI. The default is `-mno-module`.
`-mapcs-float`
  Pass floating point arguments using the float point registers. This is one of the variants of the APCS. This option is recommended if the target hardware has a floating point unit or if a lot of floating point arithmetic is going to be performed by the code. The default is `-mno-apcs-float`, since integer only code is slightly increased in size if `-mapcs-float` is used.
`-mthumb-interwork`
  Generate code which supports calling between the ARM and Thumb instruction sets. Without this option the two instruction sets cannot be reliably used inside one program. The default is `-mno-thumb-interwork`, since slightly larger code is generated when `-mthumb-interwork` is specified.
`-mno-sched-prolog`
  Prevent the reordering of instructions in the function prolog, or the merging of those instruction with the instructions in the function's body. This means that all functions will start with a recognizable set of instructions (or in fact one of a choice from a small set of different function prologues), and this information can be used to locate the start if functions inside an executable piece of code. The default is `-msched-prolog`.
`-mhard-float`
  Generate output containing floating point instructions. This is the default.
`-msoft-float`
  Generate output containing library calls for floating point. Warning: the requisite libraries are not available for all ARM targets. Normally the facilities of the machine's usual C compiler are used, but this cannot be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation.

  `-msoft-float` changes the calling convention in the output file; therefore, it is only useful if you compile all of a program with this option. In particular, you need to compile `libgcc.a`, the library that comes with GCC, with `-msoft-float` in order for this to work.

`-mfloat-abi=`name
  Specifies which ABI to use for floating point values. Permissible values are: ‘`soft`’, ‘`softfp`’ and ‘`hard`’.

  ‘`soft`’ and ‘`hard`’ are equivalent to `-msoft-float` and `-mhard-float` respectively. ‘`softfp`’ allows the generation of floating point instructions, but still uses the soft-float calling conventions.

`-mlittle-endian`
  Generate code for a processor running in little-endian mode. This is the default for all standard configurations.
`-mbig-endian`
  Generate code for a processor running in big-endian mode; the default is to compile code for a little-endian processor.
`-mwords-little-endian`
  This option only applies when generating code for big-endian processors. Generate code for a little-endian word order but a big-endian byte order. That is, a byte order of the form ‘`32107654`’. Note: this option should only be used if you require compatibility with code for big-endian ARM processors generated by versions of the compiler prior to 2.8.
`-mcpu=`name
  This specifies the name of the target ARM processor. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. Permissible names are: ‘`arm2`’, ‘`arm250`’, ‘`arm3`’, ‘`arm6`’, ‘`arm60`’, ‘`arm600`’, ‘`arm610`’, ‘`arm620`’, ‘`arm7`’, ‘`arm7m`’, ‘`arm7d`’, ‘`arm7dm`’, ‘`arm7di`’, ‘`arm7dmi`’, ‘`arm70`’, ‘`arm700`’, ‘`arm700i`’, ‘`arm710`’, ‘`arm710c`’, ‘`arm7100`’, ‘`arm7500`’, ‘`arm7500fe`’, ‘`arm7tdmi`’, ‘`arm7tdmi-s`’, ‘`arm8`’, ‘`strongarm`’, ‘`strongarm110`’, ‘`strongarm1100`’, ‘`arm8`’, ‘`arm810`’, ‘`arm9`’, ‘`arm9e`’, ‘`arm920`’, ‘`arm920t`’, ‘`arm922t`’, ‘`arm946e-s`’, ‘`arm966e-s`’, ‘`arm968e-s`’, ‘`arm926ej-s`’, ‘`arm940t`’, ‘`arm9tdmi`’, ‘`arm10tdmi`’, ‘`arm1020t`’, ‘`arm1026ej-s`’, ‘`arm10e`’, ‘`arm1020e`’, ‘`arm1022e`’, ‘`arm1136j-s`’, ‘`arm1136jf-s`’, ‘`mpcore`’, ‘`mpcorenovfp`’, ‘`arm1176jz-s`’, ‘`arm1176jzf-s`’, ‘`xscale`’, ‘`iwmmxt`’, ‘`ep9312`’.
`-mtune=`name
  This option is very similar to the `-mcpu=` option, except that instead of specifying the actual target processor type, and hence restricting which instructions can be used, it specifies that GCC should tune the performance of the code as if the target were of the type specified in this option, but still choosing the instructions that it will generate based on the cpu specified by a `-mcpu=` option. For some ARM implementations better performance can be obtained by using this option.
`-march=`name
  This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when generating assembly code. This option can be used in conjunction with or instead of the `-mcpu=` option. Permissible names are: ‘`armv2`’, ‘`armv2a`’, ‘`armv3`’, ‘`armv3m`’, ‘`armv4`’, ‘`armv4t`’, ‘`armv5`’, ‘`armv5t`’, ‘`armv5te`’, ‘`armv6`’, ‘`armv6j`’, ‘`iwmmxt`’, ‘`ep9312`’.
`-mfpu=`name
`-mfpe=`number
`-mfp=`number
  This specifies what floating point hardware (or hardware emulation) is available on the target. Permissible names are: ‘`fpa`’, ‘`fpe2`’, ‘`fpe3`’, ‘`maverick`’, ‘`vfp`’. `-mfp` and `-mfpe` are synonyms for `-mfpu`=‘`fpe`’number, for compatibility with older versions of GCC.

  If `-msoft-float` is specified this specifies the format of floating point values.

`-mstructure-size-boundary=`n
  The size of all structures and unions will be rounded up to a multiple of the number of bits set by this option. Permissible values are 8, 32 and 64. The default value varies for different toolchains. For the COFF targeted toolchain the default value is 8. A value of 64 is only allowed if the underlying ABI supports it.

  Specifying the larger number can produce faster, more efficient code, but can also increase the size of the program. Different values are potentially incompatible. Code compiled with one value cannot necessarily expect to work with code or libraries compiled with another value, if they exchange information using structures or unions.

`-mabort-on-noreturn`
  Generate a call to the function `abort` at the end of a `noreturn` function. It will be executed if the function tries to return.
`-mlong-calls`
`-mno-long-calls`
  Tells the compiler to perform function calls by first loading the address of the function into a register and then performing a subroutine call on this register. This switch is needed if the target function will lie outside of the 64 megabyte addressing range of the offset based version of subroutine call instruction.

  Even if this switch is enabled, not all function calls will be turned into long calls. The heuristic is that static functions, functions which have the ‘`short-call`’ attribute, functions that are inside the scope of a ‘`#pragma no_long_calls`’ directive and functions whose definitions have already been compiled within the current compilation unit, will not be turned into long calls. The exception to this rule is that weak function definitions, functions with the ‘`long-call`’ attribute or the ‘`section`’ attribute, and functions that are within the scope of a ‘`#pragma long_calls`’ directive, will always be turned into long calls.

  This feature is not enabled by default. Specifying `-mno-long-calls` will restore the default behavior, as will placing the function calls within the scope of a ‘`#pragma long_calls_off`’ directive. Note these switches have no effect on how the compiler generates code to handle function calls via function pointers.

`-mnop-fun-dllimport`
  Disable support for the `dllimport` attribute.
`-msingle-pic-base`
  Treat the register used for PIC addressing as read-only, rather than loading it in the prologue for each function. The run-time system is responsible for initializing this register with an appropriate value before execution begins.
`-mpic-register=`reg
  Specify the register to be used for PIC addressing. The default is R10 unless stack-checking is enabled, when R9 is used.
`-mcirrus-fix-invalid-insns`
  Insert NOPs into the instruction stream to in order to work around problems with invalid Maverick instruction combinations. This option is only valid if the `-mcpu=ep9312` option has been used to enable generation of instructions for the Cirrus Maverick floating point co-processor. This option is not enabled by default, since the problem is only present in older Maverick implementations. The default can be re-enabled by use of the `-mno-cirrus-fix-invalid-insns` switch.
`-mpoke-function-name`
  Write the name of each function into the text section, directly preceding the function prologue. The generated code is similar to this:

                     t0
                         .ascii "arm_poke_function_name", 0
                         .align
                     t1
                         .word 0xff000000 + (t1 - t0)
                     arm_poke_function_name
                         mov     ip, sp
                         stmfd   sp!, {fp, ip, lr, pc}
                         sub     fp, ip, #4

  When performing a stack backtrace, code can inspect the value of `pc` stored at `fp + 0`. If the trace function then looks at location `pc - 12` and the top 8 bits are set, then we know that there is a function name embedded immediately preceding this location and has length `((pc[-3]) & 0xff000000)`.

`-mthumb`
  Generate code for the 16-bit Thumb instruction set. The default is to use the 32-bit ARM instruction set.
`-mtpcs-frame`
  Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all non-leaf functions. (A leaf function is one that does not call any other functions.) The default is `-mno-tpcs-frame`.
`-mtpcs-leaf-frame`
  Generate a stack frame that is compliant with the Thumb Procedure Call Standard for all leaf functions. (A leaf function is one that does not call any other functions.) The default is `-mno-apcs-leaf-frame`.
`-mcallee-super-interworking`
  Gives all externally visible functions in the file being compiled an ARM instruction set header which switches to Thumb mode before executing the rest of the function. This allows these functions to be called from non-interworking code.
`-mcaller-super-interworking`
  Allows calls via function pointers (including virtual functions) to execute correctly regardless of whether the target code has been compiled for interworking or not. There is a small overhead in the cost of executing a function pointer if this option is enabled.
`-mtp=`name
  Specify the access model for the thread local storage pointer. The valid models are `soft`, which generates calls to `__aeabi_read_tp`, `cp15`, which fetches the thread pointer from `cp15` directly (supported in the arm6k architecture), and `auto`, which uses the best available method for the selected processor. The default setting is `auto`.